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ICST
2010
IEEE
13 years 8 months ago
Timed Moore Automata: Test Data Generation and Model Checking
Abstract—In this paper we introduce Timed Moore Automata, a specification formalism which is used in industrial train control applications for specifying the real-time behavior ...
Helge Löding, Jan Peleska
DATE
2007
IEEE
97views Hardware» more  DATE 2007»
14 years 4 months ago
Estimating functional coverage in bounded model checking
Formal verification is an important issue in circuit and system design. In this context, Bounded Model Checking (BMC) is one of the most successful techniques. But even if all sp...
Daniel Große, Ulrich Kühne, Rolf Drechs...
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
14 years 4 months ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...
LICS
2002
IEEE
14 years 2 months ago
Probabilistic Abstraction for Model Checking: An Approach Based on Property Testing
istic Abstraction for Model Checking: an Approach Based on Property Testing∗ Sophie Laplante† Richard Lassaigne‡ Fr´ed´eric Magniez§ Sylvain Peyronnet† Michel de Rougemo...
Sophie Laplante, Richard Lassaigne, Fréd&ea...
PLDI
2006
ACM
14 years 3 months ago
Combining type-based analysis and model checking for finding counterexamples against non-interference
Type systems for secure information flow are useful for efficiently checking that programs have secure information flow. They are, however, conservative, so that they often rej...
Hiroshi Unno, Naoki Kobayashi, Akinori Yonezawa