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» Model-integrated parallel application synthesis
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IPPS
2002
IEEE
14 years 14 days ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
IPPS
1999
IEEE
13 years 12 months ago
DEFACTO: A Design Environment for Adaptive Computing Technology
The lack of high-level design tools hampers the widespread adoption of adaptive computing systems. Application developers have to master a wide range of functions, from the high-le...
Kiran Bondalapati, Pedro C. Diniz, Phillip Duncan,...
ICS
2009
Tsinghua U.
14 years 2 months ago
High-performance CUDA kernel execution on FPGAs
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Alexandros Papakonstantinou, Karthik Gururaj, John...
BANFF
1995
13 years 11 months ago
An Automata-Theoretic Approach to Linear Temporal Logic
The automata-theoretic approach to linear temporal logic uses the theory of automata as a unifying paradigm for program specification, verification, and synthesis. Both programs ...
Moshe Y. Vardi
FCCM
2011
IEEE
220views VLSI» more  FCCM 2011»
12 years 11 months ago
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...