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DATE
1999
IEEE
172views Hardware» more  DATE 1999»
14 years 2 months ago
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
Olivier Pasquier, Jean Paul Calvez
ENTCS
2006
97views more  ENTCS 2006»
13 years 9 months ago
VyrdMC: Driving Runtime Refinement Checking with Model Checkers
This paper presents VyrdMC, a runtime verification tool we are building for concurrent software components. The correctness criterion checked by VyrdMC is refinement: Each executi...
Tayfun Elmas, Serdar Tasiran
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
14 years 1 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
IIWAS
2008
13 years 11 months ago
WEB-PerformCharts: a collaborative web-based tool for test case generation from statecharts
Distributed development of software has turned into a natural and modern approach where teams spread over the world cooperate to develop a software product, and this has become po...
Alessandro Oliveira Arantes, Nandamudi Lankalapall...
CSL
2006
Springer
14 years 1 months ago
Separation Logic for Higher-Order Store
Separation Logic is a sub-structural logic that supports local reasoning for imperative programs. It is designed to elegantly describe sharing and aliasing properties of heap struc...
Bernhard Reus, Jan Schwinghammer