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TCAD
2008
181views more  TCAD 2008»
13 years 8 months ago
A Survey of Automated Techniques for Formal Software Verification
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
Vijay D'Silva, Daniel Kroening, Georg Weissenbache...
POPL
2007
ACM
14 years 8 months ago
Proving that programs eventually do something good
In recent years we have seen great progress made in the area of automatic source-level static analysis tools. However, most of today's program verification tools are limited ...
Byron Cook, Alexey Gotsman, Andreas Podelski, Andr...
CCECE
2006
IEEE
14 years 2 months ago
A Formal CSP Framework for Message-Passing HPC Programming
To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), w...
John D. Carter, William B. Gardner
AGTIVE
2007
Springer
14 years 13 days ago
Transforming Timeline Specifications into Automata for Runtime Monitoring
Abstract. In runtime monitoring, a programmer specifies code to execute whenever a sequence of events occurs during program execution. Previous and related work has shown that runt...
Eric Bodden, Hans Vangheluwe
POPL
2005
ACM
14 years 8 months ago
Synthesis of interface specifications for Java classes
While a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequen...
P. Madhusudan, Pavol Cerný, Rajeev Alur, Wo...