18 search results - page 3 / 4 » Modeling Cache Coherence Protocol - A Case Study with FLASH |
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
SSS
2010
Springer
13 years 5 months ago
2010
Springer
We present a distributed transactional memory (TM) scheduler called Bi-interval that optimizes the execution order of transactional operations to minimize conflicts. Bi-interval c...
MOBIHOC
2003
ACM
14 years 6 months ago
2003
ACM
We develop a detailed approach to study how mobilityimpacts the performance of reactive MANET routing protocols. In particular we examine how the statistics of path durations inclu...
IEEEPACT
2003
IEEE
14 years 12 days ago
2003
IEEE
This paper presents a framework for analyzing the performance of multithreaded programs using a model called a constraint graph. We review previous constraint graph definitions fo...
PASTE
2010
ACM
14 years 6 days ago
2010
ACM
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...