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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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IPPS
1999
IEEE
14 years 26 days ago
NetCache: A Network/Cache Hybrid for Multiprocessors
In this paper we propose the use of an optical network not only as the communication medium, but also as a system-wide cache for the shared data in a multiprocessor. More specifica...
Enrique V. Carrera, Ricardo Bianchini
EUROSYS
2007
ACM
14 years 5 months ago
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
David K. Tam, Reza Azimi, Michael Stumm
PPOPP
1993
ACM
14 years 20 days ago
Integrating Message-Passing and Shared-Memory: Early Experience
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...
David A. Kranz, Kirk L. Johnson, Anant Agarwal, Jo...
SBCCI
2009
ACM
188views VLSI» more  SBCCI 2009»
14 years 3 months ago
Low-power inter-core communication through cache partitioning in embedded multiprocessors
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
Chenjie Yu, Xiangrong Zhou, Peter Petrov
NOCS
2008
IEEE
14 years 3 months ago
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...
Bart Vermeulen, Kees Goossens, Siddharth Umrani