356 search results - page 59 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
HICSS
1995
IEEE
14 years 8 days ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
CORR
2010
Springer
13 years 8 months ago
2010
Springer
Abstract--This paper focuses on data structures for multicore reachability, which is a key component in model checking algorithms and other verification methods. A cornerstone of a...
CODES
2009
IEEE
14 years 19 days ago
2009
IEEE
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...