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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
14 years 3 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
IPPS
1999
IEEE
14 years 1 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
HPCA
2011
IEEE
13 years 6 days ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
ICPP
2008
IEEE
14 years 3 months ago
Machine Learning Models to Predict Performance of Computer System Design Alternatives
Computer manufacturers spend a huge amount of time, resources, and money in designing new systems and newer configurations, and their ability to reduce costs, charge competitive p...
Berkin Özisikyilmaz, Gokhan Memik, Alok N. Ch...
TMM
2002
100views more  TMM 2002»
13 years 8 months ago
On a unified architecture for video-on-demand services
Abstract--Current video-on-demand (VoD) systems can be classified into two categories: 1) true-VoD (TVoD) and 2) near-VoD (NVoD). TVoD systems allocate a dedicated channel for ever...
Jack Y. B. Lee