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» Modeling Concurrency with Geometry
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DATE
2002
IEEE
95views Hardware» more  DATE 2002»
14 years 2 months ago
Optimal Transistor Tapering for High-Speed CMOS Circuits
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
Li Ding 0002, Pinaki Mazumder
COCOA
2009
Springer
14 years 2 months ago
Linear Coherent Bi-cluster Discovery via Line Detection and Sample Majority Voting
Discovering groups of genes that share common expression profiles is an important problem in DNA microarray analysis. Unfortunately, standard bi-clustering algorithms often fail t...
Yi Shi, Zhipeng Cai, Guohui Lin, Dale Schuurmans
SIGGRAPH
2010
ACM
14 years 2 months ago
Spatial relationship preserving character motion adaptation
This paper presents a new method for editing and retargeting motions that involve close interactions between body parts of single or multiple articulated characters, such as danci...
Edmond S. L. Ho, Taku Komura, Chiew-Lan Tai
SIGGRAPH
2010
ACM
14 years 2 months ago
Apparent layer operations for the manipulation of deformable objects
We introduce layer operations for single-view 3D deformable object manipulation, in which the user can control the depth order of layered 3D objects resting on a flat ground with...
Takeo Igarashi, Jun Mitani
SIGGRAPH
2010
ACM
14 years 2 months ago
Parameterizing subdivision surfaces
We present a method for parameterizing subdivision surfaces in an as-rigid-as-possible fashion. While much work has concentrated on parameterizing polygon meshes, little if any wo...
Lei He, Scott Schaefer, Kai Hormann