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DFT
2009
IEEE
189views VLSI» more  DFT 2009»
14 years 2 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
ASE
2005
102views more  ASE 2005»
13 years 7 months ago
Tool-Supported Verification of Product Line Requirements
A recurring difficulty for organizations that employ a product-line approach to development is that when a new product is added to an existing product line, there is currently no a...
Prasanna Padmanabhan, Robyn R. Lutz
TII
2010
113views Education» more  TII 2010»
13 years 2 months ago
An Automated Framework for Formal Verification of Timed Continuous Petri Nets
In this paper, we develop an automated framework for formal verification of timed continuous Petri nets (ContPNs). Specifically, we consider two problems: (1) given an initial set ...
Marius Kloetzer, Cristian Mahulea, Calin Belta, Ma...
BIRTHDAY
2007
Springer
13 years 11 months ago
Automating Verification of Cooperation, Control, and Design in Traffic Applications
We present a verification methodology for cooperating traffic agents covering analysis of cooperation strategies, realization of strategies through control, and implementation of c...
Werner Damm, Alfred Mikschl, Jens Oehlerking, Erns...
FM
2009
Springer
127views Formal Methods» more  FM 2009»
14 years 2 months ago
Automated Property Verification for Large Scale B Models
Michael Leuschel, Jérôme Falampin, Fa...