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CODES
2007
IEEE
14 years 3 months ago
Event-based re-training of statistical contention models for heterogeneous multiprocessors
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
CODES
2006
IEEE
14 years 3 months ago
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study
Virtual platform (ViP), or ESL (Electronic System Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case stud...
Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo L...
IJON
2000
69views more  IJON 2000»
13 years 9 months ago
PARALLEL NEUROSYS: A system for the simulation of very large networks of biologically accurate neurons on parallel computers
We present a software package for the simulation of very large neuronal networks on parallel computers. The package can be run on any system with an implementation of the Message ...
Peter Pacheco, Marcelo Camperi, Toshi Uchino
ISPASS
2009
IEEE
14 years 4 months ago
Analyzing CUDA workloads using a detailed GPU simulator
Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manyco...
Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, He...
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 11 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David