Sciweavers

85 search results - page 15 / 17
» Modeling and analysis of core-centric network processors
Sort
View
LCTRTS
2004
Springer
14 years 24 days ago
Feedback driven instruction-set extension
Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. ...
Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael ...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
DSS
2000
113views more  DSS 2000»
13 years 7 months ago
Quality of service provision in noncooperative networks with diverse user requirements
This paper studies the quality of service (QoS) provision problem in noncooperative networks where applications or users are sel sh and routers implement generalized processor sha...
K. Park, M. Sitharam, S. Chen
AINA
2007
IEEE
14 years 1 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
ADAEUROPE
2004
Springer
14 years 26 days ago
The Chance for Ada to Support Distribution and Real-Time in Embedded Systems
This paper presents a modification of GLADE —the current GNAT implementation of the Ada 95 Distributed Systems Annex (DSA)— to support the development of distributed applicatio...
Juan López Campos, J. Javier Gutiérr...