Sciweavers

85 search results - page 6 / 17
» Modeling and analysis of core-centric network processors
Sort
View
139
Voted
EMSOFT
2006
Springer
15 years 7 months ago
Modeling a system controller for timing analysis
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
Stephan Thesing
112
Voted
JPDC
2011
129views more  JPDC 2011»
14 years 10 months ago
Static timing analysis for modeling QoS in networks-on-chip
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource ...
Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Is...
243
Voted
ICDE
2006
IEEE
206views Database» more  ICDE 2006»
16 years 4 months ago
Query Co-Processing on Commodity Hardware
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
Anastassia Ailamaki, Naga K. Govindaraju, Dinesh M...
DSN
2004
IEEE
15 years 7 months ago
The Recursive NanoBox Processor Grid: A Reliable System Architecture for Unreliable Nanotechnology Devices
Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS de...
A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rang...
122
Voted
IPPS
2007
IEEE
15 years 9 months ago
A Combinatorial Analysis of Distance Reliability in Star Network
This paper addresses a constrained two-terminal reliability measure referred to as Distance Reliability (DR) between the source node u and the destination node I with the shortest...
Xiaolong Wu, Shahram Latifi, Yingtao Jiang