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NOCS
2007
IEEE
14 years 2 months ago
Fast, Accurate and Detailed NoC Simulations
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...
RTAS
2011
IEEE
12 years 11 months ago
End-to-End Delay Analysis for Fixed Priority Scheduling in WirelessHART Networks
—The WirelessHART standard has been specifically designed for real-time communication between sensor and actuator devices for industrial process monitoring and control. End-toen...
Abusayeed Saifullah, You Xu, Chenyang Lu, Yixin Ch...
PACS
2000
Springer
83views Hardware» more  PACS 2000»
13 years 11 months ago
A Comparison of Two Architectural Power Models
Reducing power, on both a per cycle basis and as the total energy used over the lifetime of an application, has become more important as small and embedded devices become increasi...
Soraya Ghiasi, Dirk Grunwald
IISWC
2008
IEEE
14 years 2 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
SAMOS
2004
Springer
14 years 1 months ago
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
Today’s Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which s...
Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Ra...