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ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
13 years 12 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
CVPR
2010
IEEE
14 years 3 months ago
Learning Shift-Invariant Sparse Representation of Actions
A central problem in the analysis of motion capture (Mo- Cap) data is how to decompose motion sequences into primitives. Ideally, a description in terms of primitives should fac...
Yi Li
ANCS
2007
ACM
13 years 11 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
BMCBI
2005
246views more  BMCBI 2005»
13 years 7 months ago
ParPEST: a pipeline for EST data analysis based on parallel computing
Background: Expressed Sequence Tags (ESTs) are short and error-prone DNA sequences generated from the 5' and 3' ends of randomly selected cDNA clones. They provide an im...
Nunzio D'Agostino, Mario Aversano, Maria Luisa Chi...
APLAS
2005
ACM
14 years 1 months ago
Integrating Physical Systems in the Static Analysis of Embedded Control Software
Interpretation interpretation is a theory of effective abstraction and/or approximation of discrete mathematical structures as found in the semantics of programming languages, mod...
Patrick Cousot