Sciweavers

222 search results - page 38 / 45
» Modeling transactional memory workload performance
Sort
View
ISCA
1996
IEEE
103views Hardware» more  ISCA 1996»
14 years 2 months ago
Evaluation of Design Alternatives for a Multiprocessor Microprocessor
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider ...
Basem A. Nayfeh, Lance Hammond, Kunle Olukotun
VLDB
1995
ACM
214views Database» more  VLDB 1995»
14 years 1 months ago
Dynamic Multi-Resource Load Balancing in Parallel Database Systems
Parallel database systems have to support the effective parallelization of complex queries in multi-user mode, i.e. in combination with inter-query/inter-transaction parallelism. ...
Erhard Rahm, Robert Marek
VEE
2005
ACM
218views Virtualization» more  VEE 2005»
14 years 3 months ago
The pauseless GC algorithm
Modern transactional response-time sensitive applications have run into practical limits on the size of garbage collected heaps. The heap can only grow until GC pauses exceed the ...
Cliff Click, Gil Tene, Michael Wolf
JSA
2000
116views more  JSA 2000»
13 years 9 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 7 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt