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» Modelling Digital Circuits Problems with Set Constraints
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ISPD
1997
ACM
142views Hardware» more  ISPD 1997»
13 years 12 months ago
Minimization of chip size and power consumption of high-speed VLSI buffers
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
D. Zhou, X. Y. Liu
DFT
2007
IEEE
105views VLSI» more  DFT 2007»
14 years 2 months ago
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output ...
Sybille Hellebrand, Christian G. Zoellin, Hans-Joa...
CSCLP
2006
Springer
13 years 11 months ago
An Attempt to Dynamically Break Symmetries in the Social Golfers Problem
A number of different satisfaction and optimisation combinatorial problems have recently been approached with constraint programming over the domain of finite sets, for increased d...
Francisco Azevedo
NORDICHI
2006
ACM
14 years 1 months ago
Affordances and constraints in screen-based musical instruments
The ixi software is an ongoing interdisciplinary research project. It focuses on the creation of screen-based interfaces as digital musical instruments. The notion of situated cog...
Thor Magnusson
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
13 years 5 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...