Minimization of chip size and power consumption of high-speed VLSI buffers

In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minimal while circuit delay is no greater than a given upper bound. The explored direction, i.e., to minimize chip area and power consumption with circuit speed as a constraint, is a more realistic setting in practical VLSI design than conventional design objectives, where minimal circuit delay is usually sought. In fact, an optimal design must achieve an expected circuit speed with minimal system resources: chip area and power consumption. By solving the formulated constrained optimization problem, signi cant improvements in chip area and power consumption are achieved.

• Type: Conference
• Year: 1997
• Where: ISPD
• Authors: D. Zhou, X. Y. Liu
• Keywords: Bu Er, Chip Area, Hardware, ISPD 1997, Power Consumption