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» Modelling Digital Circuits Problems with Set Constraints
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ISPD
1997
ACM
186views Hardware» more  ISPD 1997»
13 years 12 months ago
EWA: exact wiring-sizing algorithm
The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation. There are formal methods fo...
Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi
CEC
2007
IEEE
13 years 9 months ago
Fitness inheritance in evolutionary and multi-objective high-level synthesis
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
Christian Pilato, Gianluca Palermo, Antonino Tumeo...
ANOR
2010
106views more  ANOR 2010»
13 years 7 months ago
An ALM model for pension funds using integrated chance constraints
We discuss integrated chance constraints in their role of short-term risk constraints in a strategic ALM model for Dutch pension funds. The problem is set up as a multistage recou...
Willem K. Klein Haneveld, Matthijs H. Streutker, M...
CVPR
2009
IEEE
14 years 2 months ago
A 3D reconstruction pipeline for digital preservation
—We present a new 3D reconstruction pipeline for digital preservation of natural and cultural assets. This application requires high quality results, making time and space constr...
Alexandre Vrubel, Olga Regina Pereira Bellon, Luci...
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
14 years 1 months ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin