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» Modelling Evolvable Systems: A Temporal Logic View
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ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
15 years 8 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
PTS
2007
102views Hardware» more  PTS 2007»
15 years 6 months ago
Testing and Model-Checking Techniques for Diagnosis
Black-box testing is a popular technique for assessing the quality of a system. However, in case of a test failure, only little information is available to identify the root-cause ...
Maxim Gromov, Tim A. C. Willemse
CAISE
2008
Springer
15 years 6 months ago
Formal Modeling and Discrete-Time Analysis of BPEL Web Services
Abstract. Web services are increasingly used for building enterprise information systems according to the Service Oriented Architecture (Soa) paradigm. We propose in this paper a t...
Radu Mateescu, Sylvain Rampacek
ESOP
2003
Springer
15 years 10 months ago
Using Controller-Synthesis Techniques to Build Property-Enforcing Layers
In complex systems, like robot plants, applications are built on top of a set of components, or devices. Each of them has particular individual constraints, and there are also log...
Karine Altisen, Aurélie Clodic, Florence Ma...
FORMATS
2004
Springer
15 years 10 months ago
Symbolic Model Checking for Probabilistic Timed Automata
Probabilistic timed automata are timed automata extended with discrete probability distributions, and can be used to model timed randomised protocols or faulttolerant systems. We ...
Marta Z. Kwiatkowska, Gethin Norman, Jeremy Sprost...