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COGSR
2011
77views more  COGSR 2011»
13 years 4 months ago
Learning to use episodic memory
This paper brings together work in modeling episodic memory and reinforcement learning. We demonstrate that is possible to learn to use episodic memory retrievals while simultaneo...
Nicholas A. Gorski, John E. Laird
CGO
2009
IEEE
14 years 3 months ago
Reducing Memory Ordering Overheads in Software Transactional Memory
—Most research into high-performance software transactional memory (STM) assumes that transactions will run on a processor with a relatively strict memory model, such as Total St...
Michael F. Spear, Maged M. Michael, Michael L. Sco...
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
14 years 17 days ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
BMCBI
2007
126views more  BMCBI 2007»
13 years 9 months ago
Reconstruction of cell population dynamics using CFSE
Background: Quantifying cell division and death is central to many studies in the biological sciences. The fluorescent dye CFSE allows the tracking of cell division in vitro and i...
Andrew Yates, Cliburn Chan, Jessica Strid, Simon M...
CAV
2006
Springer
165views Hardware» more  CAV 2006»
14 years 22 days ago
Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study
Many multithreaded programs employ concurrent data types to safely share data among threads. However, highly-concurrent algorithms for even seemingly simple data types are difficul...
Sebastian Burckhardt, Rajeev Alur, Milo M. K. Mart...