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HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
14 years 1 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
TACAS
1995
Springer
94views Algorithms» more  TACAS 1995»
14 years 1 months ago
A User Guide to HyTech
HyTech is a tool for the automated analysis of embedded systems. This document, designed for the rst-time user of HyTech, guides the reader through the underlying system model, an...
Thomas A. Henzinger, Pei-Hsin Ho, Howard Wong-Toi
FPL
2004
Springer
106views Hardware» more  FPL 2004»
14 years 3 months ago
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...
Leandro Möller, Ney Laert Vilar Calazans, Fer...
ICALT
2008
IEEE
14 years 4 months ago
Deriving E-Assessment from a Competency Model
Self-assessment is a crucial component of learning. Creating effective questions is time-consuming, however, because it may require considerable resources and the skill of critica...
Onjira Sitthisak, Lester Gilbert, Hugh C. Davis
SIGMETRICS
2003
ACM
129views Hardware» more  SIGMETRICS 2003»
14 years 3 months ago
Run-time modeling and estimation of operating system power consumption
The increasing constraints on power consumption in many computing systems point to the need for power modeling and estimation for all components of a system. The Operating System ...
Tao Li, Lizy Kurian John