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IPPS
2002
IEEE
15 years 9 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
15 years 8 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
128
Voted
FPGA
2006
ACM
111views FPGA» more  FPGA 2006»
15 years 7 months ago
FPGA clock network architecture: flexibility vs. area and power
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
Julien Lamoureux, Steven J. E. Wilton
ANSS
2001
IEEE
15 years 7 months ago
New Multiprotocol WDM/CDMA-Based Optical Switch Architecture
Different switching techniques have been proposed to design optical switch architectures. Wave Division Multiplexing (WDM) techniques were extensively investigated to implement sw...
Driss Benhaddou, Ala I. Al-Fuqaha, Ghulam Chaudhry
HPCA
2003
IEEE
16 years 4 months ago
Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services
We consider the impact of different communication architectures on the performability (performance + availability) of cluster-based servers. In particular, we use a combination of ...
Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini...