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» Modelling and Evaluating Real-Time Software Architectures
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CC
2008
Springer
240views System Software» more  CC 2008»
13 years 9 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
ASPLOS
2010
ACM
14 years 1 months ago
Probabilistic job symbiosis modeling for SMT processor scheduling
Symbiotic job scheduling boosts simultaneous multithreading (SMT) processor performance by co-scheduling jobs that have ‘compatible’ demands on the processor’s shared resour...
Stijn Eyerman, Lieven Eeckhout
WSC
1997
13 years 9 months ago
A Demonstration of the Integrated Supportability Analysis and Cost System (ISACS+)
This paper describes the Integrated Supportability Analysis and Cost System (ISACS+) and the features which will be demonstrated. ISACS+ is a distributed, client/server system for...
Helena L. Weaks, James D. Barrett
CAV
2012
Springer
265views Hardware» more  CAV 2012»
11 years 10 months ago
An Axiomatic Memory Model for POWER Multiprocessors
The growing complexity of hardware optimizations employed by multiprocessors leads to subtle distinctions among allowed and disallowed behaviors, posing challenges in specifying th...
Sela Mador-Haim, Luc Maranget, Susmit Sarkar, Kayv...
COMSWARE
2007
IEEE
14 years 2 months ago
Competition between SOM Clusters to Model User Authentication System in Computer Networks
—Traditional authentication systems employed on Internet are facing an acute problem of intrusions. In this context we propose a neural architecture for user authentication throu...
Shrijit S. Joshi, Vir V. Phoha