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» Models of Computation for Networks on Chip
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IPPS
2007
IEEE
14 years 3 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
NETWORK
2011
13 years 3 months ago
Rethinking energy efficiency models of cellular networks with embodied energy
The continuous increase in energy consumption by cellular networks requires rethinking their energy efficiency. Current research indicates that one third of operating energy could...
Iztok Humar, Xiaohu Ge, Lin Xiang, Minho Jo, Min C...
ICPP
2007
IEEE
14 years 3 months ago
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
IPPS
2006
IEEE
14 years 3 months ago
Exploiting processing locality through paging configurations in multitasked reconfigurable systems
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
T. Taher, Tarek A. El-Ghazawi
ETS
2007
IEEE
109views Hardware» more  ETS 2007»
14 years 3 months ago
Test Configurations for Diagnosing Faulty Links in NoC Switches
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
Jaan Raik, Raimund Ubar, Vineeth Govind