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» Models of Computation for Networks on Chip
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MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
13 years 5 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
NOCS
2010
IEEE
13 years 6 months ago
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing
Nikita Nikitin, Satrajit Chatterjee, Jordi Cortade...
SAMOS
2005
Springer
14 years 1 months ago
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chi...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...
IWSOC
2005
IEEE
133views Hardware» more  IWSOC 2005»
14 years 1 months ago
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip
This paper presents a case study of a single-chip 3G WCDMA/FDD basestation implementation based on a circuit-switched network on chip. As the amount of transistors on a chip conti...
Daniel Wiklund, Dake Liu
DSN
2002
IEEE
14 years 15 days ago
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...