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» Models of Computation for Networks on Chip
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SDL
2003
147views Hardware» more  SDL 2003»
13 years 9 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
NIPS
2001
13 years 9 months ago
Orientation-Selective aVLSI Spiking Neurons
We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC...
Shih-Chii Liu, Jörg Kramer, Giacomo Indiveri,...
PERCOM
2008
ACM
14 years 7 months ago
A tamper-proof and lightweight authentication scheme
We present a tamper-proof and lightweight challenge-response authentication scheme based on 2-level noisy Physically Unclonable Functions (PUF). We present a security reduction, w...
Ghaith Hammouri, Erdinç Öztürk, Berk Sunar
JSA
2007
123views more  JSA 2007»
13 years 7 months ago
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Ch...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 1 months ago
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Shankar Mahadevan, Federico Angiolini, Michael Sto...