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» Models of Computation for Networks on Chip
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HOTI
2008
IEEE
14 years 3 months ago
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors
The Network-on-Chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-onchip...
Michele Petracca, Benjamin G. Lee, Keren Bergman, ...
CICC
2011
106views more  CICC 2011»
12 years 8 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
NOCS
2008
IEEE
14 years 3 months ago
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
Abstract— In this paper, we discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach i...
Zheng Shi, Alan Burns
VLSID
2002
IEEE
149views VLSI» more  VLSID 2002»
14 years 9 months ago
Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...
Sanjeev Patel
HOTI
2005
IEEE
14 years 2 months ago
High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme
A partitioned TCAM-based search engine is presented that increases packet forwarding rate multiple times over traditional TCAMs. The model works for IPv4 and IPv6 packet forwardin...
Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Pa...