6229 search results - page 34 / 1246 » Models of Computation for Networks on Chip |
DAC
1999
ACM
14 years 9 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
DCC
2010
IEEE
13 years 7 months ago
2010
IEEE
This work proposes a novel practical and general-purpose lossless compression algorithm named Neural Markovian Predictive Compression (NMPC), based on a novel combination of Bayesi...
PDP
2011
IEEE
13 years 15 days ago
2011
IEEE
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...
EUROPAR
2008
Springer
13 years 10 months ago
2008
Springer
Recent studies have showed the effectiveness of job co-scheduling in alleviating shared-cache contention on Chip Multiprocessors. Although program inputs affect cache usage and thu...
ISCA
2007
IEEE
14 years 3 months ago
2007
IEEE
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...