6229 search results - page 58 / 1246 » Models of Computation for Networks on Chip |
DAC
1999
ACM
14 years 9 months ago
1999
ACM
A 550MHz 64b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS [1]. Both th...
DAGSTUHL
2007
13 years 10 months ago
2007
Abstract. Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed eï¬...
MSWIM
2006
ACM
14 years 2 months ago
2006
ACM
KES
2008
Springer
13 years 8 months ago
2008
Springer
This paper introduces the Perplexus hardware platform, a scalable computing substrate made of custom reconfigurable devices endowed with bio-inspired capabilities. This platform w...
HPDC
2012
IEEE
11 years 11 months ago
2012
IEEE
networking with a layer 2 abstraction provides a powerful model for virtualized wide-area distributed computing resources, including for high performance computing (HPC) on collec...