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» Models of Computation for Networks on Chip
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ICDE
2006
IEEE
206views Database» more  ICDE 2006»
14 years 10 months ago
Query Co-Processing on Commodity Hardware
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
Anastassia Ailamaki, Naga K. Govindaraju, Dinesh M...
DSN
2008
IEEE
14 years 3 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
SIGCOMM
1990
ACM
14 years 27 days ago
Reliable Broadband Communication Using a Burst Erasure Correcting Code
Traditionally, a transport protocol corrects errors in a computer communication network using a simple ARQ protocol. With the arrival of broadband networks, forward error correcti...
Anthony J. McAuley
SLIP
2009
ACM
14 years 3 months ago
Prediction of high-performance on-chip global interconnection
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin...
HPCA
1996
IEEE
14 years 1 months ago
Fault-Tolerance with Multimodule Routers
The current multiprocessors such asCray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and sw...
Suresh Chalasani, Rajendra V. Boppana