Sciweavers

6229 search results - page 6 / 1246
» Models of Computation for Networks on Chip
Sort
View
CASES
2006
ACM
14 years 1 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
NOCS
2008
IEEE
14 years 1 months ago
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
Mikkel Bystrup Stensgaard, Jens Sparsø
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
14 years 24 days ago
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
In this paper, we discuss the possibility of achieving onchip fault-tolerant communication based on a new communication paradigm called stochastic communication. Specifically, for...
Radu Marculescu
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
14 years 1 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh