6229 search results - page 81 / 1246 » Models of Computation for Networks on Chip |
ERSA
2010
13 years 7 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
PDPTA
1996
13 years 10 months ago
1996
This paper describes a parallelization of the sequential dynamic programming method for solving a 2D knapsack problem where multiples of n rectangular objects are optimally packed...
DAC
1997
ACM
14 years 15 days ago
1997
ACM
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
PATMOS
2007
Springer
14 years 3 months ago
2007
Springer
BMCBI
2006
13 years 9 months ago
2006
Background: The identification of differentially expressed genes (DEGs) from Affymetrix GeneChips arrays is currently done by first computing expression levels from the low-level ...