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ICPADS
2006
IEEE
15 years 11 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
ICPPW
2006
IEEE
15 years 11 months ago
Parallel Hyperspectral Image Processing on Commodity Graphics Hardware
Many recent research efforts have been devoted to the use of commodity hardware for solving computationallyintensive scientific problems. Among such problems, hyperspectral imagi...
Javier Setoain, Christian Tenllado, Manuel Prieto,...
IEEESCC
2006
IEEE
15 years 11 months ago
Applying Distributed Business Rules - The VIDRE Approach
Today’s business processes are not static, they need to be adapted frequently to reflect changing business requirements. Several business process languages such as WS-BPEL have...
Florian Rosenberg, Christoph Nagl, Schahram Dustda...
IPPS
2006
IEEE
15 years 11 months ago
Making lockless synchronization fast: performance implications of memory reclamation
Achieving high performance for concurrent applications on modern multiprocessors remains challenging. Many programmers avoid locking to improve performance, while others replace l...
Thomas E. Hart, Paul E. McKenney, Angela Demke Bro...
MICRO
2006
IEEE
114views Hardware» more  MICRO 2006»
15 years 11 months ago
Authentication Control Point and Its Implications For Secure Processor Design
Secure processor architecture enables tamper-proof protection on software that addresses many difficult security problems such as reverse-engineering prevention, trusted computing...
Weidong Shi, Hsien-Hsin S. Lee