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ISCAS
2003
IEEE
91views Hardware» more  ISCAS 2003»
15 years 9 months ago
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity
The full-custom CMOS realization of a new modular sorting architecture is presented. The high-performance architecture is based on rank ordering, and on efficient implementation o...
Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici
IESS
2007
Springer
120views Hardware» more  IESS 2007»
15 years 10 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
ECAI
1998
Springer
15 years 8 months ago
The Neural Path to Dialogue Acts
This paper presents a neural network approach to the problem of nding the dialogue act for a given utterance. So far only symbolic, decision tree and statistical approaches were ut...
M. Kipp
ICCCN
2008
IEEE
15 years 10 months ago
The RNA Metaprotocol
— The Recursive Network Architecture (RNA) explores the relationship of layering to protocol and network architecture. RNA examines the implications of using a single, tunable pr...
Joseph D. Touch, Venkata K. Pingali
APSEC
2007
IEEE
15 years 10 months ago
E-AoSAS++ and its Software Development Environment
E-AoSAS++ is an aspect-oriented software architecture style for embedded software. It basically gives the style in which a set of state transition machines organizes a software. W...
Masami Noro, Atsushi Sawada, Yoshinari Hachisu, Ma...