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» Modular verification of code with SAT
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DFT
2009
IEEE
189views VLSI» more  DFT 2009»
14 years 2 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
CORR
2008
Springer
144views Education» more  CORR 2008»
13 years 7 months ago
Modular Compilation of a Synchronous Language
Synchronous languages rely on formal methods to ease the development of applications in an efficient and reusable way. Formal methods have been advocated as a means of increasing t...
Annie Ressouche, Daniel Gaffé, Valér...
SIGSOFT
2007
ACM
14 years 8 months ago
RELAY: static race detection on millions of lines of code
Data races occur when multiple threads are about to access the same piece of memory, and at least one of those accesses is a write. Such races can lead to hard-to-reproduce bugs t...
Jan Wen Voung, Ranjit Jhala, Sorin Lerner
CAV
2004
Springer
151views Hardware» more  CAV 2004»
13 years 11 months ago
QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings
We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models--an important step during post-silicon verification of multipro...
Ganesh Gopalakrishnan, Yue Yang, Hemanthkumar Siva...
WSC
2008
13 years 10 months ago
PLCStudio: Simulation based PLC code verification
Proposed in this paper is the architecture of a PLC programming environment that enables a visual verification of PLC programs. The proposed architecture integrates a PLC program ...
Sang C. Park, Chang Mok Park, Gi-Nam Wang, Jonggeu...