339 search results - page 43 / 68 » Modularity Analysis of Logical Design Models |
JMLR
2011
13 years 3 months ago
2011
Reports of experiments conducted with an Inductive Logic Programming system rarely describe how specific values of parameters of the system are arrived at when constructing model...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
Bounded Model Checking (BMC) relies on solving a sequence of highly correlated Boolean satisfiability (SAT) problems, each of which corresponds to the existence of counter-example...
MODELS
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. Time and timing features are an important aspect of modern electronic systems, often of embedded nature. We argue here that in early design phases, time is often of logic...
SIMUTOOLS
2008
13 years 10 months ago
2008
MIPv6 is the IPv6 based mobility management protocol and it is expected to become the mobility management protocol of choice for the Next Generation Wireless Access Networks. In o...
FDL
2007
IEEE
14 years 3 months ago
2007
IEEE
This article introduces the Time Model subprofile of MARTE, a new OMG UML Profile dedicated to Modeling and Analysis of Real-Time and Embedded systems. After a brief presentatio...