36 search results - page 5 / 8 » Multi-operand Floating-Point Addition |
ARITH
1999
IEEE
14 years 1 days ago
1999
IEEE
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
ARITH
1999
IEEE
14 years 1 days ago
1999
IEEE
This paper describes the application of high radix redundant CORDIC algorithms to complex logarithmic number system arithmetic. It shows that a CLNS addition can be performed with...
ARITH
2001
IEEE
13 years 11 months ago
2001
IEEE
Design of the leading zero anticipator ( L a ) or detector (LZD) is pivotal to the normalization of results for addition and fused multiplication-addition in highperjormance float...
EVOW
1999
Springer
13 years 12 months ago
1999
Springer
The traditional paradigm for digital filter design is based on the concept of a linear difference equation with the output response being a weighted sum of signal samples with usua...