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ISCA
2011
IEEE
486views Hardware» more  ISCA 2011»
12 years 11 months ago
Dark silicon and the end of multicore scaling
Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to wh...
Hadi Esmaeilzadeh, Emily R. Blem, Renée St....
DASIP
2010
13 years 2 months ago
High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms
Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++...
Christophe Lucarz, Ghislain Roquier, Marco Mattave...
PERCOM
2010
ACM
13 years 5 months ago
A 3-layer architecture for smart environment models
— Enriched with more and more intelligent devices modern homes rapidly transform into smart environments. Their growing capabilities enable the implementation of a new generation...
Grzegorz Lehmann, Andreas Rieger, Marco Blumendorf...
ICDE
2009
IEEE
142views Database» more  ICDE 2009»
13 years 5 months ago
Parallel Skyline Computation on Multicore Architectures
With the advent of multicore processors, it has become imperative to write parallel programs if one wishes to exploit the next generation of processors. This paper deals with skyli...
Sungwoo Park, Taekyung Kim, Jonghyun Park, Jinha K...
FCCM
2005
IEEE
93views VLSI» more  FCCM 2005»
14 years 1 months ago
Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture
This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture [3]. The register files consume a s...
Zion Kwok, Steven J. E. Wilton