7 search results - page 1 / 2 » Multilayer VLSI Layout for Interconnection Networks |
ICPP
2000
IEEE
14 years 28 days ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
SPAA
2000
ACM
14 years 3 days ago
2000
ACM
Modern VLSI processing supports a two-dimensional surface for active devices along with multiple stacked layers of interconnect. With the advent of planarization, the number of la...
GLVLSI
1996
IEEE
14 years 21 days ago
1996
IEEE
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
JOIN
2007
13 years 8 months ago
2007
In VLSI layout of interconnection networks, routing two-point nets in some restricted area is one of the central operations. It aims usually to minimize the layout area, while red...
LCN
2003
IEEE
14 years 1 months ago
2003
IEEE
Optoelectronic integrated circuits can support thousands of integrated optical laser diodes and photodetectors bonded to a high-performance CMOS substrate, and can be used in the ...