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MICRO
1997
IEEE
127views Hardware» more  MICRO 1997»
14 years 1 months ago
Exploiting Dead Value Information
We describe Dead Value Information (DVI) and introduce three new optimizations which exploit it. DVI provides assertions that certain register values are dead, meaning they will n...
Milo M. K. Martin, Amir Roth, Charles N. Fischer
CSE
2011
IEEE
12 years 8 months ago
Performance Enhancement of Network Devices with Multi-Core Processors
— In network based applications, packet capture is the main area that attracts many researchers in developing traffic monitoring systems. Along with the packet capture, many othe...
Nhat-Phuong Tran, Sugwon Hong, Myungho Lee, Seung-...
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 3 months ago
Cache aware compression for processor debug support
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...
ICIP
2000
IEEE
14 years 10 months ago
Performance Analysis of an H.263 Video Encoder for VIRAM
VIRAM (Vector Intelligent Random Access Memory) is a vector architecture processor with embedded memory, designed for portable multimedia processing devices. Its vector processing...
Thinh P. Q. Nguyen, Avideh Zakhor, Katherine A. Ye...
ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
14 years 18 days ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...