377 search results - page 49 / 76 » Multiple Instruction Stream Processor |
ICS
2001
Tsinghua U.
14 years 1 months ago
2001
Tsinghua U.
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
ICASSP
2008
IEEE
14 years 3 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
HIPEAC
2007
Springer
14 years 3 months ago
2007
Springer
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...