377 search results - page 56 / 76 » Multiple Instruction Stream Processor |
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
ICS
2004
Tsinghua U.
14 years 1 months ago
2004
Tsinghua U.
With processor speeds continuing to outpace the memory subsystem, cache missing memory operations continue to become increasingly important to application performance. In response...
LCPC
2001
Springer
14 years 4 days ago
2001
Springer
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
HPCC
2007
Springer
14 years 1 months ago
2007
Springer
To increase the scale and performance of scientific applications, scientists commonly distribute computation over multiple processors. Often without realizing it, file I/O is pa...
SODA
2008
ACM
13 years 9 months ago
2008
ACM
A common approach for dealing with large data sets is to stream over the input in one pass, and perform computations using sublinear resources. For truly massive data sets, howeve...