Sciweavers

377 search results - page 67 / 76
» Multiple Instruction Stream Processor
Sort
View
ASAP
2005
IEEE
96views Hardware» more  ASAP 2005»
14 years 1 months ago
On-Chip Lookup Tables for Fast Symmetric-Key Encryption
On public communication networks such as the Internet, data confidentiality can be provided by symmetric-key ciphers. One of the most common operations used in symmetric-key ciphe...
A. Murat Fiskiran, Ruby B. Lee
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 17 days ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
MICRO
1996
IEEE
173views Hardware» more  MICRO 1996»
13 years 11 months ago
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results
The Java bytecode language is emerging as a software distribution standard. With major vendors committed to porting the Java run-time environment to their platforms, programs in J...
Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei ...
OOPSLA
1997
Springer
13 years 11 months ago
Efficient Type Inclusion Tests
A type inclusion test determines whether one type is a subtype of another. Efficient type testing techniques exist for single subtyping, but not for languages with multiple subtyp...
Jan Vitek, R. Nigel Horspool, Andreas Krall
AIPR
2008
IEEE
13 years 9 months ago
Low-cost, high-speed computer vision using NVIDIA's CUDA architecture
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
Seung In Park, Sean P. Ponce, Jing Huang, Yong Cao...