94 search results - page 16 / 19 » Multiple-banked register file architectures |
DAC
2009
ACM
13 years 8 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
ARC
2007
Springer
13 years 11 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
ISSS
1999
IEEE
14 years 10 hour ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
SIGMETRICS
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance scheme...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...