94 search results - page 6 / 19 » Multiple-banked register file architectures |
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Many current programmable architectures designed to exploit data parallelism require computation to be structured to operate on sequentially accessed vectors or streams of data. A...
PACS
2004
Springer
14 years 1 months ago
2004
Springer
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
HPCA
2000
IEEE
14 years 4 days ago
2000
IEEE
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
DSN
2009
IEEE
2009
IEEE
Processor reliability enhancement through compiler-directed register file peak temperature reduction
13 years 11 months ago
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
APCSAC
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper proposes an approach for reducing access count to register-files based on operand data reuse. The key idea is to compare source and destination operands of the current ...