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» Multiplications of Floating Point Expansions
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ARITH
1999
IEEE
14 years 3 months ago
Multiplications of Floating Point Expansions
In modern computers, the floating point unit is the part of the processor delivering the highest computing power and getting most attention from the design team. Performance of an...
Marc Daumas
ASAP
2006
IEEE
127views Hardware» more  ASAP 2006»
14 years 26 days ago
A Cost Effective Pipelined Divider for Double Precision Floating Point Number
Abstract--The growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency, pipelined...
Sandeep B. Singh, Jayanta Biswas, S. K. Nandy
ARITH
2005
IEEE
14 years 4 months ago
Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition
In this paper we propose an architecture for the computation of the double—precision floating—point multiply—add fused (MAF) operation A + (B × C) that permits to compute ...
Javier D. Bruguera, Tomás Lang
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
14 years 5 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...
CHARME
2001
Springer
92views Hardware» more  CHARME 2001»
14 years 2 months ago
Formal Verification of the VAMP Floating Point Unit
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The ...
Christoph Berg, Christian Jacobi 0002