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APCSAC
2007
IEEE
14 years 2 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
ISCA
2008
IEEE
89views Hardware» more  ISCA 2008»
14 years 3 months ago
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this ...
Radu Teodorescu, Josep Torrellas
HIPC
2005
Springer
14 years 2 months ago
Design and Implementation of the HPCS Graph Analysis Benchmark on Symmetric Multiprocessors
Graph theoretic problems are representative of fundamental computations in traditional and emerging scientific disciplines like scientific computing, computational biology and b...
David A. Bader, Kamesh Madduri
ICS
1993
Tsinghua U.
14 years 20 days ago
Anatomy of a Message in the Alewife Multiprocessor
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-pas...
John Kubiatowicz, Anant Agarwal
ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 10 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu