60 search results - page 2 / 12 » Multithreaded Architectures and The Sort Benchmark |
IISWC
2008
IEEE
14 years 1 months ago
2008
IEEE
As multiprocessors become mainstream, techniques to address efficient simulation of multi-threaded workloads are needed. Multi-threaded simulation presents a new challenge: non-d...
IPPS
2003
IEEE
14 years 20 days ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
ISCAPDCS
2003
13 years 8 months ago
2003
Kernel coupling refers to the effect that kernel i has on kernel j in relation to running each kernel in isolation. The two kernels can correspond to adjacent kernels or a chain ...
TPDS
2010
13 years 5 months ago
2010
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
PPOPP
2010
ACM
14 years 4 months ago
2010
ACM
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...