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117
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HIPC
2005
Springer
15 years 7 months ago
Preemption Adaptivity in Time-Published Queue-Based Spin Locks
Abstract. The proliferation of multiprocessor servers and multithreaded applications has increased the demand for high-performance synchronization. Traditional scheduler-based lock...
Bijun He, William N. Scherer III, Michael L. Scott
143
Voted
QEST
2006
IEEE
15 years 8 months ago
Compositional Performability Evaluation for STATEMATE
Abstract— This paper reports on our efforts to link an industrial state-of-the-art modelling tool to academic state-of-the-art analysis algorithms. In a nutshell, we enable timed...
Eckard Böde, Marc Herbstritt, Holger Hermanns...
125
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ASPLOS
2012
ACM
13 years 10 months ago
Scalable address spaces using RCU balanced trees
Software developers commonly exploit multicore processors by building multithreaded software in which all threads of an application share a single address space. This shared addre...
Austin T. Clements, M. Frans Kaashoek, Nickolai Ze...
117
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IEEEPACT
2007
IEEE
15 years 8 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
121
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IAJIT
2011
14 years 9 months ago
Blocked-based sparse matrix-vector multiplication on distributed memory parallel computers
: The present paper discusses the implementations of sparse matrix-vector products, which are crucial for high performance solutions of large-scale linear equations, on a PC-Cluste...
Rukhsana Shahnaz, Anila Usman